This invention relates generally to computer memory systems and memory management, and more particularly to methods and systems for program directed memory access patterns.
Contemporary high performance computing main memory systems are generally composed of one or more dynamic random access memory (DRAM) devices, which are connected to one or more processors via one or more memory control elements. Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the I/O subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the memory system challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling).
FIG. 1 relates to U.S. Pat. No. 5,513,135 to Dell et al., of common assignment herewith, and depicts an early synchronous memory module. The memory module depicted in FIG. 1 is a dual in-line memory module (DIMM). This module is composed of synchronous DRAMs 8, buffer devices 12, an optimized pinout, and an interconnect and capacitive decoupling method to facilitate high performance operation. The patent also describes the use of clock re-drive on the module, using such devices as phase-locked loops (PLLs).
FIG. 2 relates to U.S. Pat. No. 6,173,382 to Dell et al., of common assignment herewith, and depicts a computer system 10 which includes a synchronous memory module 20 that is directly (i.e. point-to-point) connected to a memory controller 14 via a bus 40, and which further includes logic circuitry 24 (such as an application specific integrated circuit, or “ASIC”) that buffers, registers or otherwise acts on the address, data and control information that is received from the memory controller. The memory module 20 can be programmed to operate in a plurality of selectable or programmable modes by way of an independent bus, such as an inter-integrated circuit (I2C) control bus 34, either as part of the memory initialization process or during normal operation. When utilized in applications requiring more than a single memory module connected directly to a memory controller, the patent notes that the resulting stubs can be minimized through the use of field-effect transistor (FET) switches to electrically disconnect modules from the bus.
Relative to U.S. Pat. No. 5,513,135, U.S. Pat. No. 6,173,382 further demonstrates the capability of integrating all of the defined functions (address, command, data, presence detect, etc) into a single device. The integration of function is a common industry practice that is enabled by technology improvements and, in this case, enables additional module density and/or functionality.
FIG. 3, from U.S. Pat. No. 6,510,100 to Grundon et al., of common assignment herewith, depicts a simplified diagram and description of a memory system 10 that includes up to four registered dual inline memory modules (DIMMs) 40 on a traditional multi-drop stub bus channel. The subsystem includes a memory controller 20, an external clock buffer 30, registered DIMMs 40, an address bus 50, a control bus 60 and a data bus 70 with terminators 95 on the address bus 50 and the data bus 70. Although only a single memory channel is shown in FIG. 3, systems produced with these modules often included more than one discrete memory channel from the memory controller, with each of the memory channels operated singly (when a single channel was populated with modules) or in parallel (when two or more channels were populated with modules) to achieve the desired system functionality and/or performance.
FIG. 4, from U.S. Pat. No. 6,587,912 to Bonella et al., depicts a synchronous memory module 210 and system structure in which the repeater hubs 320 include local re-drive of the address, command and data to the local memory devices 301 and 302 via buses 321 and 322; generation of a local clock (as described in other figures and the patent text); and the re-driving of the appropriate memory interface signals to the next module or component in the system via bus 300.
Memory systems may utilize translation look aside tables in order to permit computer data to be stored in one or more storage locations best suited to data content, size and importance. Translation look aside tables (also commonly referred to as “virtual address translation tables” and “directory look aside tables”) are used to convert virtual addresses into real addresses, thus allowing the implementation of a virtual memory system. FIG. 5, from U.S. Pat. No. 3,825,904 to Burk et al., of common assignment herewith, depicts a block diagram of a translation process from a virtual address to a real address. U.S. Pat. No. 3,825,904 also describes the use of a translation look aside table that includes a virtual address and a corresponding real address for translating between virtual and real addresses.
Most high performance computing main memory systems employ multiple banks of DRAM devices that are statically configured to have a group of banks participate to support an access across a memory interface, often comprised of parallel memory channels operating in unison. The memory channels, each generally including one or more busses, may include direct connections to DRAM devices, connections to one or more interface devices that are directly connected to DRAM devices, connections to one or more interface devices that are connected to DRAM devices, and/or include one or more high speed busses connected to memory hub devices, which themselves connect directly to memory devices or one or more alternative structures. This scheme of utilizing parallel channels in unison to access a group of banks minimizes latency by having all the available bandwidth allocated to each request, usually optimized for a cache line transfer of sixty-four to two hundred fifty-six bytes. Generally, the memory controller is responsible for generating and checking the error correction code (ECC) for the data that is distributed across the one or more channels.
Some memory systems provide a configuration that partitions the memory interface and interconnected memory banks so that they are able to operate independently, in order to increase the number of concurrent independent requests serviced at a given time. This can be beneficial where critical data is transferred first and the memory system is not heavily loaded, or where accesses tend to be short and the system provides a means to truncate the access. Moreover, certain data structures are best referenced as stride address or sparse reference patterns. However, applications could benefit (e.g., from a computing application performance standpoint) from both memory system access patterns, depending on the address ranges associated with specific processing and data structures. Therefore, what is needed is the ability for a computer application to be able to dynamically switch between different memory access patterns based on attributes associated with the data.